Debug control register (DR7)

DR7 defines how the breakpoints set in Debug Address Registers should be interpreted by the processor and whether they should be interpreted at all.

The bits layout of this register is shown in the following table:

L* bits, when set to 1, enable breakpoint at the address which is specified in the corresponding Debug Address Register locally--within a task. These bits are reset by the processor on each task switch. G* bits, on the contrary, enable breakpoints globally--for all tasks, meaning that these bits are not reset by the processor.

The R/W* bits specify breakpoint conditions, as follows:

• 00: Break on instruction execution
• 01: Break when the specified address is accessed for writing only
• 10: Undefined
• 11: Break on either read or write access or when an instruction at the specified address is executed

The LEN* bits specify the size of a breakpoint in bytes, thus, allowing coverage of more than one instruction or more than one byte of data:

• 00: Breakpoint is 1-byte long
• 01: Breakpoint is 2-bytes long
• 10: Breakpoint is 8-bytes long (long mode only)
• 11: Breakpoint is 4-bytes long